Since the output is 0.2V then this is insufficient to turn on the combination of T4 and D1 which results in no current being drawn from the supply. T3 on, the base of T4 is at a potential of: Vbe3 + Vcesat2 = 0.7+0.2 = 0.9V. This type of circuit is called an The presence of both DI and R4 are essential for the reliable operation of the TTL output stage. In this case the transistor T3 is off and power consumption is low. Since R4 is only 1300 and both T4 and D1 are on then the time constant is much smaller than the DTL output circuit and hence the low-to- high delay is greatly reduced. When the output is charging, the time constant is now dependent upon the resistance of the transistor T4, diode D1 and R4. To reduce this we could just reduce the value of R3 but then the power consumption will increase when the output transistor T1 is on. ‘0’ to ‘1’)is limited by the time constant R3 x CL. Hence the delay time for the output to charge from low to high (i.e. 9.2(a) when the output changes from low to high, this capacitance (C^ has to be charged through the collector resistor R3. This could be a printed circuit board interconnect or quite simply an oscilloscope lead. At the output of all gates there is a capacitive load (CL) caused by the input capacitance of the next stage.
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